1. Field of the Invention
The present invention relates to the handling of memory access requests to shared memory in a data processing apparatus.
2. Description of the Prior Art
It is known to provide a multi-processing system in which two or more processing units, for example processor cores, share access to shared memory. Such systems are typically used to gain higher performance by arranging the different processor cores to execute respective data processing operations in parallel. Known data processing systems which provide such multi-processing capabilities include IBM 370 systems and SPARC multi-processing systems. These particular multi-processing systems are high performance systems where power efficiency and power consumption is of little concern and the main objective is maximum processing speed.
To further improve speed of access to data within such a multi-processing system, it is known to provide each of the processing units with its own local cache in which to store a subset of the data held in the shared memory. Whilst this can improve speed of access to data, it complicates the issue of data coherency. In particular, it will be appreciated that if a particular processor performs a write operation with regards to a data value held in its local cache, that data value will be updated locally within the cache, but may not necessarily also be updated at the same time in the shared memory. This is for example the case if the data value in question relates to a write back region of memory, in which case the updated data value in the cache will only be stored back to the shared memory when that data value is subsequently evicted from the cache.
Since the data may be shared with other processors, it is important to ensure that those processors will access the up-to-date data when seeking to access the associated address in shared memory. To ensure that this happens, it is known to employ a cache coherency protocol within the multi-processing system to ensure that if a particular processor updates a data value held in its local cache, that up-to-date data will be made available to any other processor subsequently requesting access to that data.
In accordance with a typical cache coherency protocol, certain accesses performed by a processor will require a coherency operation to be performed. The coherency operation will cause a notification to be sent to the other processors identifying the type of access taking place and the address being accessed. This will cause those other processors to perform certain actions defined by the cache coherency protocol. One such action is the invalidation of a cached data value, indicating that this data value has become out-of-date due to the actions of the other processors and should not be used. Such a cache coherency protocol may be administered by the provision of a snoop control unit (SCU) which monitors memory access requests issued by each of the processors and causes required actions to be taken by the processors.
In multi-processing systems where power efficiency and power consumption are considered to be important, it is known to provide a multi-processor system in which at least one of the processors is able to enter a lower power state, thus reducing the overall power consumption of the system. An example lower power mode is a dormant mode in which the standard cell logic such as the processor core is powered down completely or at least partially, but sufficient power is still supplied to a local cache within the processor, such that data values stored in that cache are maintained. Whilst this arrangement advantageously allows a multi-processor system to save power by putting processors which are temporarily not required into the dormant power mode, adherence to the cache coherency protocol is further complicated by some of the processors being in a dormant power state.
A possible approach for handling coherency operations whilst allowing some processors to enter a dormant power state involves the SCU causing a dormant processor to return to an active power state (i.e. a power state in which both the processor core and the local cache are powered) when it is required to perform certain actions defined by the cache coherency protocol. Although by this mechanism the cache coherency protocol is respected, if a processor which enters the dormant power state has several shared data items locally stored in its cache, it may be repeatedly returned to its active power state because of other processors issuing memory access requests to those data items, and the power saving benefit of putting this processor into the dormant power state may be significantly diminished. Furthermore, the latency inherent in switching a processor between power states may then result in a significant sum latency due to the repeated power state switches.
Accordingly, it would be desirable to provide a more effective solution for enabling the correct behaviour of processors in a multi-processor system with regard to the cache coherency protocol, whilst retaining the power saving benefits of being able to temporarily put one or more those processors into a dormant power state.